module MEMWB(
    input clk, rst,
    input JALFlush_from_WB,   // flush IDEX regiater

    // control signals    
    input JALFlush_from_MEM,                            // work at WB  
    input RegWrite_from_MEM, MeMtoReg_from_MEM,          // work at WB
    
    // data
    input [31:0] JalAddr_from_MEM,                 // work at WB    
    input [31:0] pc8_from_MEM,                     // work at WB    
    input [4:0]  rd_from_MEM,                      // work at WB
    input [31:0] Res_from_MEM,                     // work at WB
    input  overflow_from_MEM,                      // work at WB
    input [31:0] Data_from_dcache,                 // work at WB

    // out
    output reg JALFlush_2_WB,                            // work at WB  
    output reg RegWrite_2_WB, MeMtoReg_2_WB,          // work at WB
    
    // data
    output reg [31:0] JalAddr_2_WB,                 // work at WB    
    output reg [31:0] pc8_2_WB,                     // work at WB    
    output reg [4:0]  rd_2_WB,                      // work at WB
    output reg [31:0] Res_2_WB,                     // work at WB
    output reg  overflow_2_WB,                      // work at WB
    output reg [31:0] Data_2_WB                  // work at WB    
);
always@(posedge clk or negedge rst)begin
    if(!rst)begin
        JALFlush_2_WB <= 1'b0;                             // work at WB  
        RegWrite_2_WB <= 1'b0; 
        MeMtoReg_2_WB <= 1'b0;  
        JalAddr_2_WB <= 32'd0;                 // work at WB    
        pc8_2_WB <= 32'd0;                    // work at WB    
        rd_2_WB <= 5'd0;                      // work at WB
        Res_2_WB <= 32'd0;                     // work at WB
        overflow_2_WB <= 1'd0;                      // work at WB
        Data_2_WB  <= 32'd0;
    end else begin
        JALFlush_2_WB <= JALFlush_from_MEM;                             // work at WB  
        RegWrite_2_WB <= RegWrite_from_MEM; 
        MeMtoReg_2_WB <= MeMtoReg_from_MEM;  
        JalAddr_2_WB <= JalAddr_from_MEM;                 // work at WB    
        pc8_2_WB <= pc8_from_MEM;                    // work at WB    
        rd_2_WB <= rd_from_MEM;                      // work at WB
        Res_2_WB <= Res_from_MEM;                     // work at WB
        overflow_2_WB <= overflow_from_MEM;                      // work at WB
        Data_2_WB  <= Data_from_dcache;
    end
end

endmodule